In U.S. Pat. No. 4,287,433 Steven N. Goodspeed introduced the basic dual phase splitter TTL circuit configuration useful for example in TTL output buffers and output devices. Such TTL output buffer circuits have an output for delivering data signals of high and low potential, a pulldown transistor element for sinking current from the output to ground, a pullup transistor element for sourcing current to the output from a power supply, and a phase splitter transistor element operatively coupled to the pullup and pulldown transistor elements. The phase splitter transistor element controls the conducting states of the respective pullup and pulldown transistor elements in accordance with signals at the input of the buffer circuit. According to the Goodspeed invention, multiple phase splitter transistor elements are coupled substantially in parallel configuration between the input and the pulldown transistor element. Typically, dual phase splitters, i.e., two phase splitter transistor elements, are incorporated in the buffer circuit or output device. However as used in this specification and in the claims the word "dual" is intended to mean "multiple" and to include either two or more transistor elements.
One of the dual phase splitters, designated for example the output phase splitter transistor element, is coupled to both the pullup and pulldown transistor elements for "phase splitting". The output phase splitter transistor element simultaneously controls the pullup and pulldown transistor elements in opposite conducting states in response to input signals. The emitter nodes of the dual phase splitter transistor elements are jointly coupled in parallel to control the pulldown transistor element. The base drives are also coupled in parallel. However, only the collector node of the output phase splitter transistor element is coupled to the pullup transistor element. The collector node of the secondary or supplemental phase splitter transistor element is available to perform other circuit functions disconnected from the pullup transistor element and the output.
For example in the Goodspeed U.S. Pat. No. 4,287,433 the output phase splitter transistor element coupled to both the pullup and pulldown transistor elements is in turn coupled to the power supply V.sub.cc through a relatively high collector resistance. The collector node of the secondary phase splitter transistor element, disconnected from the pullup transistor element, is coupled to the power supply V.sub.cc through a relatively low collector resistance. The dual phase splitter transistor elements jointly define in parallel a relatively low collector resistance path from high potential. The current derived from this parallel path drives the pulldown transistor element for transition from high to low potential at the output and for maintaining the low potential state at the output of the device.
For a tristate TTL output device the enable gate is coupled to the base nodes of the dual phase splitter transistor elements and to the base of the node pullup transistor element. The enable gate provides a route to ground for disabling the various transistor elements in the high impedance third state. Because of the dual phase splitter configuration, however, the collector node of the secondary phase splitter transistor element with the relatively low collector resistance is not connected to the enable gate. Power consumption in the high impedance third state is therefore reduced and restricted to the small current passing through the relatively high collector resistance path of the output phase splitter transistor only.
In U.S. Pat. No. 4,255,670 the dual phase splitter TTL circuit configuration is used to accelerate sinking of current from the output to ground during transition from high to low potential at the output. A supplemental feedback circuit is coupled between the output and the collector node of the secondarY phase splitter transistor element to drive the pulldown transistor element to greater conduction. Only the output phase splitter transistor element is coupled to both the pullup and pulldown transistor elements The enable gate is coupled to the base of the pullup transistor element at the collector node of the output phase splitter transistor only. The secondary phase splitter transistor element therefore blocks a path from the output to ground that would otherwise occur through the feedback circuit and through the enable gate. The use of dual phase splitters effectively disconnects the supplemental feedback circuit and output from the enable gate.
Such an application of the dual phase splitter circuit configuration however introduces a variable collector current through one of the dual phase splitter transistor elements. The dual phase splitter transistor elements are generally coupled in current mirror configuration, that is with the base nodes and emitter nodes respectively tied together in parallel. The current mirror configuration establishes equal emitter current densities through the transistor elements. With different or varying collector current to one of the transistor elements, the transistor with the lesser collector current may draw all of the base drive current in the process of equalizing emitter current densities, a phenomenon known as "current hogging". Such current hogging may effectively offset or negate the benefits of the supplemental circuit function performed by the secondary phase splitter transistor element. In the case of the tristate output feedback circuit, current hogging can destroy .beta..sup.2 amplification and acceleration of sinking current from the output intended by the use of the feedback circuit.
More generally, in a current mirror configuration of multiple transistor elements, at least one of the transistor elements is arranged in the circuit with a fixed collector load and substantially constant emitter current density. This transistor element is referred to herein as the primary or reference transistor element, or the output transistor element. In the case of dual phase splitter TTL buffer and output circuits it is typically the output phase splitter transistor element. The other current mirror transistor element or elements may have a variable collector load and are referred to herein as the secondary or supplemental transistor elements. In the case of dual phase splitter TTL buffers and output devices it is typically referred to herein as the secondary phase splitter transistor element. The substantially constant emitter current density of the primary reference transistor element is "mirrored" in the emitter current density of the secondary transistor elements. It is in the process of "mirroring" that the variable collector load secondary phase splitter transistor elements may "hog" the base drive current and deprive the primary transistor element of necessary base drive current.
The problem of current hogging in dual phase splitter transistor element TTL circuits is resolved by David A. Ferris et.al. in U.S. Pat. No. 4,661,727 by departing from the current mirror configuration for the dual phase splitter transistor elements. Ferris et.al. provide independent base drives to multiple phase splitter transistor elements in a TTL tristate output circuit to prevent current hogging. The output phase splitter transistor element is coupled to both the pullup and pulldown transistor elements while the secondary phase splitter transistor element is coupled in the output feedback circuit to accelerate sinking of current through the pulldown transistor element with .beta..sup.2 amplification of current. Separate and independent input base drive transistor elements are provided at the base of each phase splitter transistor element to prevent current hogging. This dual phase splitter TTL circuit configuration with independent base drives at the dual phase splitters is applied to advantage by Geoff Hannington in U.S. Pat. No. 4,677,320 for an ECL to TTL translator.
The present invention provides a novel circuit of dual transistor elements in current mirror configuration without current hogging. It also implements a novel application of the circuit as a dual phase splitter transistor element TTL output circuit to resolve problems encountered in the basic JK flip flop circuit and to improve the JK flip flop circuit operating characteristics. The problems in conventional JK flip flop circuits resolved by the present invention are briefly summarized as follows.
The invention is applied in the basic JK flip flop in order to solve the problem of feedback transistor breakdown encountered in conventional JK flip flops and to enhance generally the JK flip flop operating characteristics. The basic JK flip flop circuit is provided with J and K input circuits for receiving input signals of high and low potential. The J and K input circuits are also referred to as the "master" input circuits. Q and Q output buffer circuits have respective inputs operatively coupled to the respective J and K input circuits for controlling the states of the Q and Q outputs according to the J & K input signals. The Q and Q output circuits are also referred to as the "slave" output circuits. Each of the Q and Q output buffer circuits incorporate the elements of the standard TTL output circuit with a single phase splitter.
A first cross feedback circuit and first cross feedback transistor element is coupled between the J input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit. A second cross feedback circuit and second cross feedback transistor element is coupled between the K input circuit and a collector node of the phase splitter transistor element of the Q output buffer circuit. CLOCK, SET and CLEAR signal inputs are also provided. The logical operation of the JK flip flop is summarized in Table 1 as follows:
TABLE 1 ______________________________________ JK FLIP FLOP TRUTH TABLE J K Q.sub.n+1 .sup.-- Q.sub.n+1 ______________________________________ 0 0 Q.sub.n .sup.-- Q.sub.n 1 0 1 0 0 1 0 1 1 1 .sup.-- Q.sub.n Q.sub.n ______________________________________
The subscript n designates the present cycle or event at clock pulse n, while the subscript n+1 designates the next cycle or event after clocking, at clock pulse n+1.
When either of the outputs Q or Q is at high potential, the emitter of the corresponding cross feedback transistor is also pulled to the high potential level by the collector of the single phase splitter. The high voltage reverse bias at the emitter may result in emitter collector breakdown and emitter base breakdown of the cross feedback transistor as hereafter described in further detail. The reverse conduction at the cross feedback transistor may pulldown the output to a potential level below specifications. It also degrades AC switching speeds of the JK flip flop.